Nana Sutisna
Papers
7
Total Citations
38
H-Index
3
About
Nana Sutisna is a researcher specializing in hardware acceleration for machine learning, reinforcement learning (RL) algorithms, and embedded intelligent systems. His work sits at the intersection of computer architecture and artificial intelligence, with a particular focus on designing efficient, scalable hardware implementations of RL algorithms for real-world applications. Sutisna's most significant contribution is the development of FARANE-Q (Fast Parallel and Pipeline Q-Learning Accelerator), a configurable RL accelerator implemented as a System on Chip (SoC). This innovative architecture offers flexibility, scalability, and high computation speed, earning over 20 citations and establishing itself as a notable reference in hardware-accelerated machine learning. Building on this foundation, he extended his work to MazeCov-Q, an RL accelerator tailored for coverage-based navigation tasks, and applied Q-learning principles to FPGA-based mobile robot control systems, demonstrating practical deployment in robotics contexts. More recently, Sutisna has expanded into computer vision-driven robotics, contributing to exploration robots powered by the YOLOv8 object detection algorithm for search-and-rescue applications. Collectively, his research reflects a consistent drive to bridge advanced machine learning techniques with efficient, deployable hardware solutions, making him a valuable contributor to the growing field of intelligent embedded systems.
Research Focus
Key Achievements
Top Papers
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- 4Control System for Mobile Robot using FPGA-Based Q-Learning Accelerator3 citations · 2022
- 5Exploration Robot Based On YOLOv8 Algorithm2 citations · 2024
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