Hardware acceleration

Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator

Daniel Neil, Shih‐Chii Liu

Citations: 256 • 2014

DeepBurning

Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li

Citations: 208 • 2016

Embedded Streaming Deep Neural Networks Accelerator With Applications

Ayşegül Dündar, Jonghoon Jin, Berin Martini, Eugenio Culurciello

Citations: 122 • 2016

Evolution of the Graphics Processing Unit (GPU)

William J. Dally, Stephen W. Keckler, David B. Kirk

Citations: 105 • 2021

Review of ASIC accelerators for deep neural network

Raju Machupalli, Masum Hossain, Mrinal Mandal

Citations: 75 • 2022

The microarchitecture of a real-time robot motion planning accelerator

Sean Murray, William Floyd-Jones, Qi Ying, George Konidaris, Daniel J. Sorin

Citations: 58 • 2016

Semi-dense SLAM on an FPGA SoC

Konstantinos Boikos, Christos-Savvas Bouganis

Citations: 48 • 2016

Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous Platforms

Yuan Meng, Sanmukh R. Kuppannagari, Viktor K. Prasanna

Citations: 46 • 2020

StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network

Gang Chen, Yehua Ling, Tao He, Haitao Meng, Shengyu He, Yu Zhang, Kai Huang

Citations: 45 • 2020

FPGA based acceleration and deceleration circuit for industrial robots and CNC machine tools

Jae Wook Jeon, Yun-Ki Kim

Citations: 43 • 2002

Robomorphic computing: a design methodology for domain-specific accelerators parameterized by robot morphology

Sabrina M. Neuman, Brian Plancher, Thomas Bourgeat, Thierry Tambe, Srinivas Devadas, Vijay Janapa Reddi

Citations: 42 • 2021

FPGA Architectures for Real-time Dense SLAM

Q Gautier, Alric Althoff, Ryan Kastner

Citations: 33 • 2019

An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics

Vanderlei Bonato, Rafael Peron, Denis F. Wolf, Jose Arnaldo Mascagni de Holanda, Eduardo Marques, João M. P. Cardoso

Citations: 33 • 2007

GPU optimization of the SGM stereo algorithm

Istvan Haller, Sergiu Nedevschi

Citations: 32 • 2010

FPGA acceleration of multilevel ORB feature extraction for computer vision

Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond

Citations: 31 • 2017

Offloaded Execution of Deep Learning Inference at Edge: Challenges and Insights

S. Dey, Jayeeta Mondal, Arijit Mukherjee

Citations: 29 • 2019

An SoC-FPGA-Based Iterative-Closest-Point Accelerator Enabling Faster Picking Robots

Atsutake Kosuge, Keisuke Yamamoto, Yukinori Akamine, T. Oshima

Citations: 28 • 2020

π-BA: Bundle Adjustment Hardware Accelerator based on Distribution of 3D-Point Observations

Qiang Liu, Shuzhen Qin, Yu Bo, Jie Tang, Shaoshan Liu

Citations: 28 • 2020

The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation

K. Sridharan, T.K. Priya

Citations: 27 • 2005

MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator for Mobile VSLAM

Ye Liu, Jingyuan Li, Kun Huang, Xiangting Li, Xiuyuan Qi, Liang Chang, Yu Long, Jun Zhou

Citations: 24 • 2022