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About

Ben Oliveau is a computer architect whose research focuses on domain-specific accelerators for machine learning and robotics, with a particular emphasis on near-memory computing and heterogeneous system-on-chip (SoC) design. His most notable contribution is the NeCTAr (Near-Cache Transformer Accelerator) project, a 16nm heterogeneous multicore RISC-V SoC that integrates both near-core and near-memory accelerators to efficiently handle sparse and dense machine learning kernels. The prototype chip, operating at 400MHz at 0.85V, achieves 109 GOPS for matrix-vector multiplications, demonstrating significant performance gains for language model inference and robotic workloads. This work, published in 2024, has already garnered 5 citations, reflecting its timely relevance in the rapidly evolving field of efficient AI hardware. Oliveau’s research addresses the critical challenge of memory-bound computations in AI systems, offering a practical path toward more energy-efficient and high-performance edge computing solutions. His contributions are particularly valuable for students and researchers exploring the intersection of computer architecture, machine learning, and robotics, where hardware-software co-design is key to unlocking next-generation intelligent systems.