Ken Ho
Papers
1
Total Citations
5
H-Index
1
About
Ken Ho is a leading figure in computer architecture, specializing in the design of energy-efficient accelerators for machine learning and robotics. His work bridges the gap between near-core and near-memory computing, with a focus on sparse and dense neural network kernels. Ho’s most notable contribution is the NeCTAr (Near-Cache Transformer Accelerator) and RASoC system-on-chips, introduced in his highly cited 2024 paper. These heterogeneous multicore RISC-V SoCs, fabricated in Intel 16nm technology, achieve groundbreaking performance—running at 400MHz and delivering 109 GOPS for matrix-vector multiplications—while maintaining low power consumption at 0.85V. This work demonstrates how near-memory acceleration can dramatically improve inference efficiency for large language models and robotic control. With over 5 citations in just its first year, Ho’s research is already shaping next-generation edge AI hardware. His achievements highlight a rare ability to prototype complex chip designs, making him a key innovator in post-Moore’s law computing. For students and researchers, Ho’s work offers a blueprint for balancing performance, power, and area in specialized accelerators.
Research Focus
Key Achievements
Top Papers
- 1