Teppei Nakano

Kyushu Institute of Technology, Waseda University

Papers

Total Citations

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About

Teppei Nakano is a researcher whose work bridges the fields of hardware-efficient neural network design and networked robotics. His most cited contribution, "A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture" (2003, 29 citations), introduced a pioneering approach to implementing convolutional neural networks directly on chip. By merging analog and digital circuitry, Nakano’s architecture offered a path toward low-power, high-speed image recognition—an early and influential step in the development of hardware accelerators for deep learning. This work remains a touchstone for researchers exploring neuromorphic and mixed-signal VLSI systems. Nakano also contributed to robotics software engineering with his proposal of MONEA (Message-Oriented NEtworked-robot Architecture, 2006). This framework addressed the growing complexity of multifunctional robots by providing a modular, message-passing development environment, aiming to streamline integration and reduce system-level conflicts. While his citation counts are modest, Nakano’s work demonstrates a forward-looking vision: combining efficient hardware design with scalable software architectures. His research is particularly relevant for students and engineers interested in the intersection of embedded AI, custom hardware, and robot system design.