Marcela Leite

Universidade do Estado de Santa Catarina

Papers

Total Citations

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About

Dr. Marcela Leite is a researcher at the intersection of model-driven engineering and hardware description, with a focus on bridging high-level system specifications and low-level implementation. Her work centers on the integration of aspect-oriented modeling with UML/MARTE to address crosscutting non-functional concerns in embedded and real-time systems. In her most cited work, "On Generating VHDL Descriptions from Aspect-Oriented UML/MARTE Models," she introduced a methodology for automatically producing VHDL code from high-level models that incorporate aspect-oriented semantics, enabling the separation of functional requirements from crosscutting concerns like timing, power, or fault tolerance. This contribution is particularly valuable for complex system-on-chip designs, where modularity and traceability are critical. While her citation count is modest, her research represents a foundational step in automating hardware synthesis from abstract models, offering a pathway to more efficient design workflows. Dr. Leite’s work is especially relevant for researchers exploring the convergence of software engineering practices—such as aspect-oriented programming—with hardware description languages, and it continues to inform discussions on model-to-text transformations in the embedded systems community.