Joo Peng Teh

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About

Joo Peng Teh is a researcher whose work sits at the intersection of hardware acceleration and machine vision, with a primary focus on real-time image processing for robotic systems. Her key research area centers on the FPGA implementation of log-polar mapping, a biologically inspired, spatially-variant image representation technique that mimics the human retina’s foveal architecture. Teh’s major contribution lies in demonstrating how this mapping can be efficiently realized on field-programmable gate arrays, enabling significant data compression and faster sampling rates—critical for active vision systems in tracking applications. Her most-cited paper, “FPGA Implementation of Log-polar Mapping” (2008), has accumulated 8 citations, while a subsequent 2010 version added 2 more, reflecting sustained interest in her hardware-oriented approach. This work directly addresses the need for faster image-processing speeds in machine vision, making it valuable for robotics and autonomous systems. Teh’s achievements showcase a practical engineering mindset, bridging theoretical vision algorithms with real-time hardware solutions. Her research remains relevant for students and engineers seeking to optimize vision pipelines through custom digital logic, offering a foundation for further exploration in embedded computer vision and neuromorphic hardware design.