Systolic array
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Residue arithmetic VLSI array architecture for manipulator pseudo-inverse Jacobian computation
Po-Hsuan Chang, C.S.G. Lee
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Warp: A Programmable Systolic Array Processor
H. T. Kung, O. Menzilcioglu
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Systolic architectures for the manipulator inertia matrix
Masoud Amin-Javaheri, David E. Orin
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Parallel VLSI architectures for real-time kinematics of redundant robots
Ian D. Walker, Joseph R. Cavallaro
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A systolic/cellular computer architecture for linear algebraic operations
J.G. Nash
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Compiler optimizations for asynchronous systolic array programs
Monica S. Lam
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A programmable real-time systolic processor architecture for image morphological operations, binary template matching and min/max filtering
M. Djunatan, Tati Rajab Mengko
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A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA
Leandro de Souza Rosa, Aravind Dasu, Pedro C. Diniz, Vanderlei Bonato
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Extending the CMU Warp Machine with a Boundary Processor
Marco Annaratone, E. Arnould, P. Hsiung, H. T. Kung
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A parallel algorithm and architecture for the control of kinematically redundant manipulators
A.A. Maciejewski, J.M. Reagin
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PANTHER: a parallel neuro-systolic architecture for real-time processing
M.I. Patel, Meghna Ranganathan
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High-speed 2-D hardware convolution architecture based on VLSI systolic arrays
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Impact of VLSI on Pattern Recognition and Image Processing
Tzay Y. Young, Philip S. Liu
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Fast implementation of direct robot kinematics with cordic systolic arrays
B.G. Mertzios
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