Towards Automatic Migration of ROS Components from Software to Hardware

Abstract

I. INTRODUCTION The use of the ROS middleware is a growing trend in robotics in general, in particular in experimental branches of robotics such as modular robotics, fields robotics, and the vast area of cyber-physical systems (for example applied to welfare technology). Our main area of interest is in experimental robotics and cyber-physical systems. When building “robot controllers” for the aforementioned systems there are numerous suitable technological platforms. Given specific requirements we can choose an appropriate standardized approach, for example emphasizing flexibility and ease of development by using a generic middleware — such as ROS — or emphasizing real-time performance and direct hardware access by using approaches based on dedicated, embedded hardware. So far ROS and hard real-time embedded systems have however not been easily uniteable while retaining the same overall communication and processing methodology at all levels. In this paper we present an approach aimed at tackling the schism between high-level, flexible software and lowlevel, real-time software. The key idea of our approach is to enable software components written for a high-level publish-subscribe software architecture to be automatically migrated to a dedicated hardware architecture implemented using programmable logic. Our approach is based on the Unity framework, a unified software/hardware framework based on FPGAs for quickly interfacing high-level software to low-level robotics hardware. The vision of Unity is to enable non-expert users to build high-quality interface and control systems using FPGAs and to interface them to highlevel software frameworks, thereby providing a framework for speeding up and increasing innovation in experimental robotics. This paper presents the overall vision and the initial work on the implementation of an architecture supporting a generative approach, based on a declarative specification of how software components are mapped to a hardware architecture; the actual language design is left as future work.