CoDANet: Hardware-Aware Neural Architecture Search for Optimized Deep Learning on FPGAs

Abstract

Deep neural networks have significantly advanced scientific discovery and engineering. However, their substantial computational and storage requirements hinder deployment on resource-constrained systems, particularly robotics and edge intelligence, where efficiency and low latency are essential. Herein, we present CoDANet, a hardware-aware Neural Architecture Search (NAS) framework designed to optimize neural network models for FPGA deployment by balancing network performance with hardware resource utilization. By integrating hardware feed-back into the NAS process, CoDANet simultaneously enhances network accuracy and optimizes FPGA resource usage. Experiments demonstrate that CoDANet achieves substantial reductions in hardware consumption across various scenarios, such as an 85.3% reduction in Lookup Table (LUT) usage with only a 1.6% decrease in AUC under performance-prioritized settings. These results highlight CoDANet's effectiveness in designing neural networks tailored for efficient deployment on robotics and edge systems.