Architecturally-efficient computation of shortest paths for a mobile robot

Abstract

The computation of shortest path for a mobile robot to get to a destination is considered in this paper. An architecturally-efficient solution is presented for this problem. Results of implementation in Xilinx Virtex FPGA are promising: the solution operates at approximately 72 MHz and the implementation for a graph with 40 nodes and 52 edges fits in one XCV3200E-FG1156 device.