Vulnerability Analysis and Risk Assessment for SoCs Used in Safety-Critical Embedded Systems

Abstract

Intelligent systems, such as intelligent automotive systems or intelligent robots, require a rigorous reliability/safety while the systems are in operation. As system-on-chip (SoC) becomes more and more complicated, the SoC could encounter the reliability problem due to the increased likelihood of faults or radiation-induced soft errors especially when the chip fabrication enters the very deep submicron technology [Baumann, 2005; Constantinescu, 2002; Karnik et al., 2004; Zorian et al., 2005]. SoC becomes prevalent in the intelligent safetyrelated applications, and therefore, fault-robust design with the safety validation is required to guarantee that the developed SoC is able to comply with the safety requirements defined by the international norms, such as IEC 61508 [Brown, 2000; International Electrotechnical Commission [IEC], 1998-2000]. Therefore, safety attribute plays a key metric in the design of SoC systems. It is essential to perform the safety validation and risk reduction process to guarantee the safety metric of SoC before it is being put to use.