High Performance Computing for Precision Landing and Hazard Avoidance and Co-Design Approach

Abstract

The Safe and Precise Landing Integrated Capabilities Evolution (SPLICE) project continues NASA's technology development for Precision Landing and Hazard Avoidance (PL&HA). The High-Performance Space Computing (HPSC) project manages a contract to build a multi core processor that is intended to be NASA's computing platform for future human and robotic spaceflight missions. This paper describes the flight computer for the PL&HA payload that will be used in SPLICE flight testing onboard suborbital rockets. This computer is being designed as a surrogate architecture for the HPSC chip, using a Xilinx Multi-Processor System on a Chip (MPSoC). Field testing with the surrogate architecture facilitates cross-agency experience with the HPSC and positions projects for future technology infusion opportunities. The MPSoC is hosted on a custom baseboard and interfaced to a second custom board that provides the sensor and vehicle interfaces. Early design trades for the SPLICE surrogate implementation are described. Preliminary performance testing on the surrogate platform using an optical navigation algorithm developed for the Orion vehicle is described, and shows 2.5 times execution speedup resulting from minimal modifications to the original code. In general, High Performance Computing/Embedded Computing (HPC/HPEC) required to address computational challenges in a wide range of NASA missions has consistently had challenges in implementation due to the diversity in the disciplines required to develop a solution. Typically, algorithm designers with expertise in the physics of the problem, and numeric approaches to solving the relations that model the physics, do not have expertise in processing architectures. There are strong dependencies between the overall performance of the system and the choices made in the modeling of the physics, the numerical approaches to solutions for the physical relations, and how these operations are mapped to computational resources in an architecture. To address this concern, a Model-Based Systems Engineering (MBSE) based concept for conducting multi-disciplinary co-design of the Guidance, Navigation, and Control (GN&C) algorithms, processing hardware configuration, and system software is introduced.