Design and Implementation of a 64-bit RISC Processor Using VHDL

Abstract

In the present paper, we present the design and implementation of a 64-bit reduced instruction set (RISC) processor with built-in-self test (BIST) features. A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Key features of the design including its architecture, datapath, and instruction set are presented. The design is implemented using VHDL and verified on Xilinx ISE simulator. The processor is designed keeping in mind specific applications. The proposed design may find applications where automation and control is required.Illustrations highlight the typical use of our processor in bottling plants and control of robotic movements using exhaustive simulations. Future applications may include its use in vending machines, ATMs, mobile phones, and portable gaming kits.