A High-Precision Clock Synchronization System for the CEPC Accelerator

摘要

The Circular Electron Positron Collider (CEPC) distributes a reference clock distributed to 192 control nodes along its 100~km underground tunnel. The required synchronization precision is 30~ps (standard deviation). We present an enhanced White Rabbit (WR)-based clock synchronization system designed to meet this requirement. A noise-budget analysis of the standard WR slave loop identifies the analog actuation chain (DAC + VCXO + multiplier PLL) and restart-induced timing uncertainty as the dominant limitations. In our redesigned node, the DAC+VCXO chain is replaced by a Si5345A DSPLL clock generator with DCO-based phase control, removing the board-level analog tuning stage. GTX transceiver phase alignment and manual byte-alignment fixing reduce restart uncertainty from 88.8~ps to 12~ps peak-to-peak. For multi-node operation, we introduce a cascaded global-control architecture with PC-side PID auto-tuned by TD3 reinforcement learning, on-chip-temperature feed-forward calibrated to $-0.76\,\mathrm{ps}/^\circ\mathrm{C}$. The measured point-to-point synchronization precision is 3.38~ps over 1~m fiber and 3.92~ps over 50~km. In a 12-level cascade, the end-node precision reaches 6.66~ps at constant temperature and 7.30~ps under a 13$\,^\circ$C temperature swing. Synchronized-clock TIE jitter stays below 1~ps regardless of cascade depth. Restart uncertainty is 2.82~ps (std.\ dev.). A 4-level cascade operated stably for 25 hours of continuous monitoring. All measured metrics fall well within the CEPC 30~ps budget.