Conservative Design with High-Performance COTS Architectures - Beyond Traditional Approaches

摘要

Safety-critical industrial systems are subject to many stringent requirements, including non-functional design constraints that are essential for robustness, reliability, and safety. System timing is often treated as an afterthought, even though data age, race conditions, or missed deadlines can affect functional safety. This challenge has been addressed in real-time system design, but the situation has worsened in recent system designs. Many applications require high performance to achieve behavioral safety goals, i.e., safety of intended functionality, using complex heterogeneous architectures with multi-level memory, interconnected chiplets, and accelerators based on the latest technologies. Machine learning applications in factory automation, robotics, and autonomous systems are important examples. The timing of such architectures is heavily influenced by the physical effects of temperature control and chip variations, including aging, leading to even more complex chip-specific software execution timing. The paper shows that identical chips differ in their timing behavior, and that most of the timing variation of a single chip can be effectively modeled using additive white Gaussian noise. We explain how such timing behavior can be exploited in high-assurance design for safety and reliability, following established reliability analysis, test, and redundancy techniques.