Parallel algorithms for robot path planning with simpler VLSI architecture

Abstract

This paper proposes a parallel algorithm for robot path planning on a linear array with a reconfigurable pipelined bus system (LARPBS) through the construction of a Voronoi diagram on a binary image of the workspace. The algorithm is based on a d4 distance metric, and it does not incur any additional time or processor requirements compared with those of a previously reported proposal (Tzionas et al., 1997). This paper recommends the same model as the simpler VLSI architecture for the problem in question.