Reliable Hardware Architectures of the CORDIC Algorithm With a Fixed Angle of Rotations

Abstract

Fixed-angle-rotation operation of vectors is widely used in signal processing, robotics, and graphics. Various optimized coordinate rotation digital computer (CORDIC) designs have been proposed for uniform rotation of vectors through known and specified angles. Nevertheless, in the presence of faults, such hardware architectures are potentially vulnerable. In this brief, we propose efficient error detection schemes for cascaded single-rotation CORDIC which hamper the performance of the architectures negligibly. We present signature-based schemes for this CORDIC variant to detect both transient and permanent faults. We further present how such schemes can be applied to other variants of CORDIC. The effectiveness of the proposed designs is assessed through field-programmable gate array implementations and error simulations. The results give confidence for the proposed efficient architectures which can be tailored based on the reliability requirements and overhead tolerance.