Implementation of SM4 on FPGA: Trade-Off Analysis between Area and Speed

Abstract

The security of robot wireless communication has become increasingly important when it performs sensitive tasks. It is common to encrypt the control signal and data to avoid malicious monitoring. This paper studies SM4 block cipher algorithm and proposes multiple hardware designs based on FPGA to explore the trade-off between area and speed. Compared to published solutions on the same platform, the resource-first design improves the throughput rate by 54% at the expense of 25% resource utilization increased. The speed-first design with fully pipeline achieves 6% improvement in speed with 4% resource utilization saved. In addition, three balanced designs are implemented to analyze the relationship between area and speed. This work can define the upper and lower bound of performance of SM4 which provides guidance on choosing the proper hardware scheme for designers. At last, we encapsulate designs into the IP cores of SM4 for future work in robot network security.