FPGA-based parallel hardware architecture for SIFT algorithm

Abstract

A parallel hardware architecture for real-time image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm has been presented. The proposed parallel hardware architecture is completely stand-alone; it reads the input data directly from VITA2000 and provides the results via a Field-Programmable Gate Array (FPGA); image key points are extracted in combination with SIFT IP Core. Our proposed parallel hardware system could be able to detect feature points up to 30 frames per second with the resolution 1920*1080; the proposed method has the similar accuracy to PC implementation. Experimental results shown that the hardware architecture for SIFT algorithm realizes fast feature extraction, the shortcomings of massive calculation and low speed in the process of extracting image features have been efficiently improved, which meets the real-time requirements in feature matching system. The achieved system performance is at least two orders of magnitude better than a PC-based solution; this algorithm can be applied to feature matching in the field of Robotics.