High Level Synthesis of ROS Protocol Interpretation and Communication Circuit for FPGA

Abstract

This paper proposes a method with encapsulating hardware description on ROS nodes for improving the productivity of robot development. To realize intellectual robots, we should satisfy constraints involving high performance, low power consumption, and high energy efficiency. FPGA (Field Programmable Gate Array) is well-known to satisfy the constraints. In conventional methods, to apply FPGA into software description of ordinary ROS system, we need to describe codes for performing the conversion process between the abstraction level of the ROS message level and the abstraction degree of the low FPGA level. Thus, the describing cost causes to the productivity problem. This proposal contributes to simplifying the describing part of FPGA in the conversion process. In this process, we provide a generating mechanism from C/C++ programs into circuits in High-Level Synthesis and integrating communication in the ROS protocol. To evaluate whether the method contributes to productivity, we compare a C/C++ program in the new method with a conventional description in HDL. As a result, the size of the new method was 127 lines, while the conventional was 860 liens. Therefore, we consider this method contributes to improving productivity.