cReComp: Automated Design Tool for ROS-Compliant FPGA Component

Abstract

Autonomous mobile robots require high-performance computation to meet variety of requirements of functions, such as sensing, intelligent image processing and controlling actuators. We focus on FPGA as a hardware platform for autonomous mobile robot system. However, a FPGA-based system is not effective in development cost, since it requires HDL-based design whose productivity is relatively low. In order to solve this problem, we have already proposed a design principle of ROS-compliant FPGA component, which is effective in easy integration of a FPGA device into any robot system. Although it allows ROS-based software to access easily to hardware circuitry in FPGA, high development cost of HDL-based circuitry still remains as a large problem. So, in this paper, we propose cReComp which is an automated design tool to improve productivity of ROS-compliant FPGA component. cReComp generates codes of interface software and hardware automatically. We evaluate cReComp from two major aspects: improvements in design productivity, and operation speed of generated FPGA components by cReComp. Experimental results show that only less than one hour is enough for novice designers to implement a ROS-compliant FPGA component into programmable SoC. Furthermore, our results reveal that generated FPGA component operates 1.85 times faster than the original software-based component.