An SoC-FPGA-Based Iterative-Closest-Point Accelerator Enabling Faster Picking Robots

Abstract

The conventional picking robots suffered from low picking throughput due to a large amount of computation of the object-pose-estimation algorithm which is called iterative-closest-point (ICP) algorithm. This article presents an field-programmable gate array (FPGA)-based ICP accelerator, which achieves 11.7-times-faster object-pose estimation by a picking robot compared with the state-of-the-art technique based on K-D-tree <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -nearest neighbor (NN) search and four-core CPU. To accelerate the ICP, both algorithm-level and hardware-level techniques have been proposed and developed. The former is a hierarchical-graph-based <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> -NN search enabling simultaneous acquisition of plural neighboring points. The latter is a sorting-network-based circuit implemented on an system on a chip (SoC)-FPGA. In addition, dynamic structural reconfiguration between the two key functionalities (graph generation and nearest neighbor search) is explored by utilizing the partial reconfiguration capability of FPGA to save the required hardware resource. Experiments of the proposed FPGA-based ICP accelerator using Amazon Picking Challenge data sets have confirmed that the object-pose estimation by ICP takes only 0.72 s at the power consumption of 4.2 W.