Investigation and Reduction of Systematic Defects by Wafer Backside Process in Nanometer Semiconductor Manufacturing

Abstract

The research aims at wafer front side defects causing by faulty back sides during the semiconductor manufacturing. The rapid semiconductor development of semiconductor technology comes with the extremely tight control of SPC and small tolerance of defects even the defects in wafer backside could cause the fail of front side chips while technologies entered nanometer node. The wafer backside be polluted and damaged repeatedly by mechanical chucks or robots during manufacturing processes, and which combined with gas or liquid chemical processes could make uneven produce marks. The formation mechanism of the abnormal backside condition was investigated, and the corresponding front side's defect condition was drawn out. In Cu backend, backside clean is required to remove metal ions, however, the difference of acid etching rate on poly silicon and silicon nitride would lead to the abnormal leveling of lithography. Optimizing chemical formulation can improve backside leveling obviously.