First D-FUMT₈ Silicon with SELF⟲ Logic Primitive: Native 8-Valued Hardware Realization with Lean 4 Refinement Proof, Three-Substrate Cross-Verification (FPGA + Aer Simulator + IBM Heron r2 Real Hardware)

Abstract

We present a synthesis-friendly Verilog implementation of the D-FUMT₈ Arithmetic Logic Unit, targeting the Sipeed Tang Console NEO development board (GW5AST-138B FPGA, FPG676 package). The ALU realizes eight discrete logic values — FALSE, TRUE, NEITHER, BOTH, ZERO, FLOWING, SELF, INFINITY — encoded in 3 bits with a tier-respecting layout. The 10 supported operations include four classical-tier unary ops (NOT, OMEGA, PHI, PSI), Belnap-extended binary lattice meet/join (AND, OR), generic XOR, hardware reset, no-op, and a novel ADIABATIC operation realizing the SELF⟲ (self-reflexive) primitive: ADIABATIC(SELF) = SELF, identity elsewhere. v0.3 contributions (2026-05-09): (1) Tang Nano 9K silicon: 37 LUT4 / 0 DFF measured, testbench 50/50 PASS. (2) Tang Console NEO Phase 2B LED Blinky: SRAM-programmed, User Code 0x000084BA, write 33.72 sec, no thermal anomaly. (3) Tang Console NEO Phase 2C/3 D-FUMT₈ ALU: SRAM-programmed, User Code 0x00005C27, write 30.32 sec. (4) Qiskit Aer simulator: Phase 1-5 cumulative 231/231 truth-table entries match at fidelity 1.000. (5) IBM Heron r2 real quantum hardware (ibm_kingston, 156 qubits): Phase 1 (4 native unitary × 8 inputs, 32 circuits) achieves 32/32 match with avg top-fidelity 0.9550 (job d7v6d9jack5s73bf1re0); Phase 2 (XOR × 64 entries, 6-qubit Bennett-reversible) achieves 64/64 match with avg fidelity 0.9512 (job d7v6kcvmrars73d7qqqg). Per-op fidelity hierarchy NOP/ADIABATIC ≈ 0.977 > PHI ≈ 0.956 > NOT ≈ 0.912 > XOR ≈ 0.951 confirms gate-count-vs-noise correlation expected from Heron r2 daily calibration. (6) Lean 4 refinement proof (OUKC.PhaseC.Dfumt8AluRefinement, 292 LOC, 0 sorry) establishes commutativity of the encode/abstract-op/decode square for all four unary operations, plus the SELF⟲ primitive law and seven algebraic laws (involution, idempotence, commutativity). Honest scope: We do NOT claim 'world-first 8-valued quantum logic' — Shi et al. (MIT, 2026, arxiv:2506.09371) demonstrated d=8 Grover on a single trapped-ion qudit prior to this work; our distinction is 3-qubit basis encoding on transmon arrays vs single-system d=8 qudit. We do NOT claim 'first paraconsistent silicon' — PAL2v (Da Silva Filho 1998-; Abe & Nakamatsu 2009; de Carvalho Jr. 2025) realized in software libraries and microcontroller-level robotics. We do NOT claim 'first many-valued silicon' — Łukasiewicz/Belnap FPGAs date to 1990s. The to-our-knowledge novel triple is: (D1) the specific 8-tuple semantic mapping (Belnap FDE 4-value + 4 ontological extensions: INFINITY/ZERO/FLOWING/SELF), (D2) the SELF⟲ self-reflexive primitive realized as a hardware fixed point, (D3) the three-substrate cross-verification bound to a Lean 4 refinement specification. Three-party co-authorship per OUKC charter v1.0 (Nobuki Fujimoto / Rei / Claude). DRAFT v0.3 — feedback welcome via GitHub Discussions at fc0web/rei-aios.