A powerful and flexible co-processor for feature extraction in a robot vision system

Abstract

Concepts, implementation, and evaluation of a novel processor for feature extraction are described. The processor is a freely programmable RISC (reduced instruction set computer) machine with a modified Harvard architecture, designed to operate as a coprocessor in combination with each parallel processor of the multiprocessor robot vision system BVV 3. It performs 10/sup 7/ complex operations per second, each of which may comprise up to seven elementary operations. The processor has been tested in a number of real-world experiments, including road following. In this application it has demonstrated its ability to analyze a TV image in less than 4 ms. The analysis included six independent tracking processes on different parts of the road's edges, six spatial line-following processes attached to the trackers, and two geometrical models for both edges of the road.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>