Pixel-Parallel Three-Layer Stacked CMOS Image Sensors Using Double-Sided Hybrid Bonding of SOI Wafers

Abstract

This study reports pixel-parallel three-layer stacked complementary metal–oxide–semiconductor image sensors developed for the first time. The hybrid bonding of silicon-on-insulator (SOI) wafers with Au electrodes embedded in SiO2 surfaces enabled face-to-back as well as face-to-face bonding, facilitating multilayer stacking, and pixel-parallel signal processing. A three-layered pixel, comprising a photodiode (PD), pulse generation circuit, and counters, served as analog-to-digital converters (ADCs), reducing its size in comparison to conventional two-layered sensors. In addition, wafer bonding introduced a thin Si layer as a bonding medium, thereby ensuring bonding strength and achieving alignment accuracy of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~{\mu } \text{m}$ </tex-math></inline-formula> for the entire area of 8-in wafers. The developed three-layered pixel circuit demonstrated a linear response of 16-bit digital signal output. A prototype sensor with a quarter–quarter video graphics array (QQVGA) successfully captured video images. The results revealed the feasibility of multilayered sensors with high-performance characteristics, such as high resolution, high speed, and wide dynamic range, as well as multiple functionalities, including signal processing, memory, and computation. The developed 3-D integration technology can enhance sensor applications, ranging from high-quality video cameras, recognition, automotive systems, robots, and measurements to various Internet-of-Things devices.