A Programmable Parallel Processor Architecture in FPGAs for Image Processing Sensors

摘要

In industrial image processing real-time requirements are very important issues. In future robot assistants, for example, object detection below 10 ms will be indispensable. This can only be met by over-sized DSP-/microcontroller working in a pixel serial manner with a high system clock. In this paper we present a parallel processor architecture, which is based on a self-designed soft IP processor cell. It is applicable for multiple object detection in industrial image processing with reconfigurable hardware. The processors are connected by a NEWS network and programmable by means of an assembler language. They can fulfil multiple algorithms such as the simple erosion or the summation of pixels. This summation leads to the calculation of moments and allows the determination of the centroid as well as the rotation angle of objects. Contrary to a fully parallel architecture, the image here is processed piece by piece so that a Spartan-3 1000 FPGA is sufficient for the whole design. The greatest advantages of our approach are the short processing time (20 MPixel/s), the small design size and the low clocking. Nevertheless, multiple objects in an image can be handled and our solution is much cheaper than comparable DSP-/microcontroller ones.