System-Level fault Injection in System Design Platform

摘要

Intelligent systems, such as intelligent car driving system or intelligent robot, require a stringent dependability while the systems are in operation. As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry while the SoC fabrication enters the very deep submicron technology. In this paper, we present a new approach of system-level fault injection in SystemC design platform, which can be used to validate the robustness of the SoC. The framework of fault injection proposed consists of the following levels of abstraction: bus-cycle accurate level, untimed functional transaction-level modeling with primitive channel sc_fifo, and timed functional transaction-level modeling with hierarchical channel. We demonstrate the feasibility of the proposed fault injection framework with the modules of a system modeled at different levels of abstraction as described above.