FPGA Design and Implementation of Multi-Filtering Techniques U sing Flag-Bit and Flicker Clock

摘要

Real time system is a condition where the processor is required to perform its tasks within a certain time constraints of some processes or simultaneously with the system it is assisting. Typically, it suffers from two main problems; delay in data processing and complexity of the decision-making process. The delay is caused by reasons such as computational power, processor unit architecture, and synchronization signals in the system. To improve the performance of these systems in term of processing power, a new architecture and clocking technique is realized in this paper. This new architecture design called Embedded Parallel Systolic Filters (EPSF) that process data gathered from sensors and landmarks are proposed in our study using a high-density reconfigurable device (FPGA chip). The results expose that EPSF architecture and bit-flag with a flicker clock achieve appreciably better in multiple input sensors signal under both incessant and interrupted conditions. Unlike the usual processing units in current tracking and navigation systems used in robots, this system permits autonomous control of the robot through a multiple technique of filtering and processing. Furthermore, it offers fast performance and a minimal size for the entire system that minimizing the delay about 50%.