Simulation of a computer with variable hardware and variable instruction set

摘要

Parallel processing systems are used today in many applications such as in vision, robotics, real-time processes etc. It is therefore important to develop simulators to aid automated design of parallel-processing systems. This Paper discusses development of a Meta-simulator for simulating and analyzing such systems. This could form a part of a general multi-processor system CAD package. The statistical results derived using the simulator can be used to generate Reduced Instruction Set Computing (RISC) elements providing reduced hardware complexity and improved overall system performance. Two methods of implementation - namely using, Instruction Set Processing Specification, ISPS and High Level Language, C are reviewed and compared. Evaluation of candidate architectures requires use of high level and assembly languages for writing benchmark programs for the simulator. We therefore discuss the notion of Meta-Assembler and Meta-Compiler also.